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| CoreU1PHY - UTOPIA Level 1 PHY Interface Product Summary Intended Use * Standard UTOPIA Level 1 PHY Interface to any ATM Link-Layer Device * - - * Libero IDE and Industry Standard Synthesis and Simulation Tools RTL Version VHDL Source Code Core Synthesis and Simulation Scripts Actel-Developed Testbench (VHDL) Fully Supported by Industry-Standard Simulation Tools Key Features * Standard 8-Bit, 25 MHz UTOPIA Level 1 PHY Interface Complies with the ATM Forum UTOPIA Specification, Level 1 Version 2.01 (af-phy0017.000) Separate TX and RX Clocks and Interface Pins Supports Cell-Level Handshake for 53- or 54-byte ATM Cells with Automatic Add/Drop of UDF2 Field in the ATM Header in 53-byte Mode 16-Bit (54-byte) User Interfaces Can be Used Directly or Bolt-Up to One of Actel's ATM Cell Buffer Blocks: ATMBUFx Design Tools Support * * Simulation: VITAL Compliant VHDL and OVI Compliant Verilog Simulators Synthesis: LeonardoSpectrum(R), Synplify(R), Design Compiler(R), FPGA CompilerTM, and FPGA ExpressTM * * Contents General Description ................................................... Device Requirements ................................................. UTOPIA Interface ....................................................... User Interface ............................................................. Ordering Information ................................................ List of Changes ........................................................... Datasheet Categories ................................................. 1 2 2 4 6 7 7 * Supported Families * * * * Fusion ProASIC3/E ProASICPLUS(R) Axcelerator(R) Core Deliverables * Netlist Version - Compiled RTL Simulation Model Fully Supported in Actel Libero(R) Integrated Design Environment (IDE) Structural VHDL and Verilog Netlists (with and without I/O Pads) Compatible with Actel's General Description CoreU1PHY is a UTOPIA Level 1 PHY interface core that connects directly to any ATM link-layer (master) device and user logic (or optional ATM cell buffer blocks) to provide an interface between the link-layer device and a non-standard physical layer device (Figure 1). - TX Utopia Level 1 Link-Layer Device CoreATMBUF3 RX CoreU1PHY CoreATMBUF3 User Logic Other Device Figure 1 * Block Diagram December 2005 (c) 2005 Actel Corporation v 4 .0 1 CoreU1PHY - UTOPIA Level 1 PHY Interface Device Requirements CoreU1PHY can be implemented in either the ProASICPLUS or Axcelerator device families. Table 1 indicates the number of core logic cells required in each technology. Table 1 * Device Utilization and Performance Cells or Tiles Family Fusion ProASIC3/E ProASIC PLUS Total Utilization Device AFS060 A3P060 APA075 AX125 Percentage 8.0% 8.0% 4.5% 6.0% Performance 25 MHz 25 MHz >25 MHz >25 MHz Sequential 59 59 79 60 Combinatorial 61 61 58 60 Axcelerator UTOPIA Interface CoreU1PHY implements a standard 8-bit point-to-point physical-layer interface that supports cell lengths of either 53 or 54 bytes. If the cell_size bit is low, a 53-byte cell is transferred and the UDF2 byte is inserted on ingress to and dropped on egress from the user interface; otherwise, 54 bytes are transferred. The UTOPIA interface signals are summarized in Table 2. Table 2 * UTOPIA Interface Signals Signal u1_tx_clk u1_tx_clav u1_tx_en u1_tx_soc u1_tx_data u1_rx_clk u1_rx_clav u1_rx_en u1_rx_soc u1_rx_data Type Description In Out In In In In Out In Out Out TX interface clock Active high cell buffer space available Active low data transfer enable Active high start-of-cell indication 8-bit ingress data RX interface clock Active high cell buffer space available Active low data transfer enable Active high start-of-cell indication 8-bit ingress data CoreU1PHY will then look for u1_tx_soc to become active (high), indicating that the first word of the cell transfer is active on the bus. As shown in Figure 2, u1_tx_soc may be asserted during the same cycle that u1_tx_en is driven low. Once u1_tx_soc is recognized, the core accepts 53 bytes (or 54) and forwards them to the user interface. u1_tx_clk u1_tx_clav u1_tx_en u1_tx_soc u1_tx_data Figure 2 * TX Start of Cell H1 H2 If the link-layer device does not have another cell to send, or if polling during the current cell transfer indicates that the CoreU1PHY is not ready to accept another cell, the U1 link-layer may deselect the physical interface by de-asserting u1_tx_en after the last word of the transfer (Figure 3). u1_tx_clk u1_tx_clav u1_tx_en u1_tx_soc u1_tx_data P51 P52 P53 P54 XX TX Interface (Ingress) The process of transferring a cell on the UTOPIA level 1 TX interface begins with u1_tx_clav. The core asserts u1_tx_clav high whenever w_avail is asserted at the user interface. If u1_tx_clav is low, the link-layer device must wait until CoreU1PHY indicates that it is ready to receive another cell. To begin sending cells on the TX interface, the link-layer simply asserts u1_tx_en low (Figure 2). Figure 3 * TX Transfer Complete 2 v4.0 CoreU1PHY - UTOPIA Level 1 PHY Interface Alternatively, the link-layer device may choose to stall inbetween cells without deselecting the physical interface, as illustrated in Figure 4. u1_tx_clk u1_tx_clav u1_tx_en u1_tx_soc u1_tx_data P51 P52 P53 P54 XX H1 H2 The CoreU1PHY will then assert u1_rx_soc high, indicating that the first word of the cell transfer is active on the bus. Once a transfer has begun, all 53 or 54 bytes of the cell are transferred without interruption. If polling during the current transfer indicates that there are no more cells available, or if the link-layer is unable to receive another cell from the CoreU1PHY, the linklayer may deselect the physical interface by de-asserting u1_rx_en after receiving the last byte of the current cell, as illustrated in Figure 7. u1_rx_clk Figure 4 * TX Stalled by u1_tx_clav u1_rx_clav u1_rx_en u1_rx_soc u1_rx_data P51 P52 P53 P54 XX If the link-layer has another cell to send to the physical interface and if polling during the current cell indicates that the CoreU1PHY is able to accept another cell, the link-layer may send cells back-to-back, as illustrated in Figure 5. Figure 7 * RX End of Transfer u1_tx_clk u1_tx_clav u1_tx_en u1_tx_soc u1_tx_data P51 P52 P53 P54 H1 H2 H3 H4 H5 H6 Figure 5 * TX Back-to-Back Transfer If the link-layer continues to enable the CoreU1PHY during the last two bytes of the current cell transfer, and one or more complete ATM cells are ready to be transferred (u1_rx_avail is high), the CoreU1PHY will send back-to-back cells, as shown in Figure 8. If the user interface indicates r_avail low (no data to send), but the link-layer continues to assert U1_rx_en low, the CoreU1PHY interface will remain idle until r_avail is asserted high on the user interface and another cell transfer begins. u1_rx_clk u1_rx_clav u1_rx_en u1_rx_soc u1_rx_data P51 P52 P53 P54 H1 H2 H3 H4 H5 RX Interface (Egress) The RX interface operates in a similar manner. The process begins with u1_rx_clav. If the user interface indicates there is at least one complete cell available for transfer by asserting r_avail high, the core responds with u1_rx_clav high; otherwise, u1_rx_clav is asserted low and the link-layer device must wait until the user logic indicates that a cell is available for transfer. To begin receiving cells on the RX interface, the linklayer must select the CoreU1PHY by asserting u1_rx_en low (Figure 6). u1_rx_clk u1_rx_clav u1_rx_en u1_rx_soc u1_rx_data Figure 6 * RX Start of Cell Transfer Figure 8 * RX Back-to-Back Transfer H1 H2 v4.0 3 CoreU1PHY - UTOPIA Level 1 PHY Interface User Interface The user interface can connect directly to Actel's CoreATMBUF3 cell buffer, an intellectual property core that provides buffering for up to three 54-byte ATM cells in each direction (Figure 1 on page 1). Alternatively, the designer may choose to connect his/her own cell buffer or user logic function directly to the user interface. The signals associated with the user interface are summarized in Table 3. Table 3 * User Interface Signals Signal reset xlate w_avail w_phy_act w_enable w_adr w_data r_avail r_buf_en r_adr r_data Type Description In In In Out Out Out Out In Out Out In Active high - resets all registers 53 / 54-byte cell size control Active high - user ready to receive Active high physical selected Active high data enable 5-bit word count 16-bit data bus Active high - user ready to send Active high read enable 5-bit word count 16-bit data bus signals and data for the read interface are associated with the u1_rx_clk. Each interface is controlled from the user logic by the w_avail and r_avail signals, respectively. When the cell buffer or user logic is ready to receive or send a cell on either interface, the user must assert x_avail high. In turn, this will cause the CoreU1PHY to assert u1_x_clav to the link-layer device. Write Interface (ingress) Whenever the link-layer asserts u1_tx_en low, the w_phy_act signal is asserted high to indicate that the ingress user interface is active. The w_enable signal will remain low until the link-layer begins to transfer a cell. Since the CoreU1PHY translates from 8-bit data at the UTOPIA interface to 16-bit data at the user interface, w_enable is asserted for one clock cycle while a data word is valid. W_adr is incremented on the next risingedge of u1_tx_clk, and then w_enable is de-asserted for one clock cycle (except during insertion of the UDF2 byte, as shown in Figure 9). W_adr increments from 00 to 1B hex (27 words). U1_tx_clk U1_tx_clav U1_tx_en U1_tx_soc U1_tx_data w_phy_act w_enable w_adr w_data XX 00 01 02 03 P1P2 XX H1 H2 H3 H4 H5 P1 P2 P3 When reset is asserted high, all registers in the CoreU1PHY are cleared. They will remain in this state as long as reset is asserted. If the xlate input is low, the CoreU1PHY will transfer data to/from the link-layer device as 53-byte ATM cells. On ingress (TX), the CoreU1PHY will duplicate the fifth byte of the ATM header and insert it as the sixth byte (UDF2) in order to create a standard 54-byte ATM cell on the user "write" interface. Conversely, the CoreU1PHY will accept a standard 54-byte cell at the user "read" interface and drop the sixth byte during transfer to the egress (RX) interface. If xlate is high, no translation is performed; 54-byte cells are transferred on all interfaces. The user interface is divided into write (TX) and read (RX) interfaces. The control signals and data for the write interface are associated with the u1_tx_clk, while control H1H2 XX H3H4 H5H5 XX Figure 9 * Write Interface Cell Transfer If the address resets to 00 hex before reaching 1B hex, the cell transfer was interrupted by the link-layer and the previous bytes of the cell should be dropped. When w_adr reaches 1B hex, a complete 54-byte cell has been received. The w_adr will reset to 00 hex and w_enable is de-asserted until another cell transfer begins. The w_phy_act signal is not de-asserted unless the link-layer deselects the CoreU1PHY by asserting u1_tx_en high. 4 v4.0 CoreU1PHY - UTOPIA Level 1 PHY Interface Read Interface (egress) When r_avail is asserted high at the user interface and the u1_rx_en signal is asserted low by the link-layer, the CoreU1PHY will begin accepting data on the user interface. Once a cell transfer has begun, the CoreU1PHY will transfer 27 words of data regardless of the state of r_avail. The CoreU1PHY asserts r_buf_en high, expecting to accept data at the r_data inputs on the next risingedge of u1_rx_clk as illustrated in Figure 10. accepted on the following rising edge of u1_rx_clk, and the r_adr is incremented. Then r_buf_en is de-asserted for one clock cycle except after the third data word when xlate is low (53-byte mode), or when a back-to-back read operation is needed in order to get the first payload byte in time. The cycle is repeated until r_adr reaches 1B hex and the last two bytes of the ATM cell are sent. At this point, r_adr is reset to 00 hex, and if r_avail indicates that another cell is immediately available, and u1_rx_en remains low, the CoreU1PHY will immediately begin sending the next cell as shown in Figure 11. Otherwise, r_buf_en remains low until the CoreU1PHY begins to transmit another cell. U1_rx_cl U1_rx_cla U1_rx_en U1_rx_soc U1_rx_data r_buf_en r_adr r_data 00 XX 01 H1H2 02 H3H4 03 H5H6 04 P1P2 XX H1 H2 H3 H4 H5 P1 P2 U1_rx_cl U1_rx_clav U1_rx_en U1_rx_soc U1_rx_data R_avail r_buf_en r_adr1B r_data 00 XX 01 H1H2 02 H3H4 03 H5H6 04 P1P2 P47 P48 H1 H2 H3 H4 H5 P1 P2 Figure 10 * Read Interface Cell Transfer The CoreU1PHY provides r_adr as a word count (00 to 1B hex) and increments whenever the core accepts data at the r_data pins. Since the CoreU1PHY translates from 16bit data at the user interface to 8-bit data at the UTOPIA interface, r_buf_en is asserted for one clock cycle, data is Figure 11 * Back-to-Back Read Cell Transfer v4.0 5 CoreU1PHY - UTOPIA Level 1 PHY Interface Ordering Information Order CoreU1PHY through your local Actel sales representative. Use the following numbering convention when ordering: CoreU1PHY-XX, where XX is listed in Table 4. Table 4 * Ordering Codes XX EV SN AN SR AR UR Description Evaluation Version Netlist for single-use on Actel Devices Netlist for unlimited use on Actel devices RTL for single-use on Actel Devices RTL for unlimited use on Actel devices RTL for unlimited use and not restricted to Actel devices 6 v4.0 CoreU1PHY - UTOPIA Level 1 PHY Interface List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v 4 .0 ) v3.0 The "Supported Families" section was updated to include Fusion. Table 1 was updated to include Fusion data. v2.0 The "Supported Families" section was added. Table 1 * Device Utilization and Performance was updated. Page 1 2 1 2 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. v4.0 7 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 5172171-2/12.05 |
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